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The Plastic Encapsulated Microcircuit Initiative is being developed and managed by the Manufacturing Technologies Division, US Army Aviation and Missile Command. The objective of this initiative is to enhance, demonstrate, and implement standardized processes for a coating system for integrated circuits (ICs) at the wafer level to provide near hermetic capabilities regardless of the packaging approach used. Required shelf life of Army missiles range from 10-20 years under a variety of uncontrolled storage conditions. Current plastic encapsulated microcircuits (PEMs) have not proven reliable under long term unpowered storage in harsh environments, and conclusive data on PEMs capabilities in this area will not be available for 3-10 years. During that time period, PEMs will be inserted into weapon systems for cost savings or due to parts nonavailability due partially to DMSMS . A process is needed that provides moisture and ionic contamination protection to nearly the same level (less than 2% failures after 1000 hours of Highly Accelerated Temperature and Humidity Stress Test - HAST) as currently achieved by hermetic devices. Thrusts of this MTO are: selection of a high-performance/low cost coating material; improvements to current processes to reduce costs of inline coating at the wafer level; determination of yield enhancements and other benefits resulting from the coating to incentivize integrated circuit (IC) manufacturers to implement the coating process; and, leveraging of Program Management (PM) funds to prove, through long term and accelerated testing, that the coating provides sufficient protection to PEMs used in their systems.
Initial results under an Air Force S&T program show near hermetic protection capabilities for Dow Corning's ChipSeal TM , and a 1-10% increase in part yield due to greater resistance to scratching provided by the coating. Primary savings to PMs will be the ability to use low cost PEMs (as low as 1/10 the cost of the equivalent hermetic part) for a much broader range of applications than previously allowed and lower life cycle costs (vs. standard PEMs) due to longer shelf life parts and less field failures. The goal is to select a material with a minimum 98% survival rate in HAST in FY00, demonstrate a coating process for the chip sealing at less than $200 per wafer in FY01, and demonstrate the chip sealing process on one or more industry semiconductor chip fabrication lines with data validating the predetermined exit requirements in FY02.
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